1. Field of the Invention
The present invention generally relates to circuits for controlling the phase of signals, and particularly relates to a phase control circuit which generates a clock signal having a desired phase by combining a plurality of clock signals.
2. Description of the Related Art
In order to improve system performance, not only the speed of individual components such as processors and memories need to be enhanced, but also the speed of signal transmission between the individual components, i.e., chips, needs to be enhanced. In order to increase the speed of signal transmission, the circuits that receive signals need to operate at accurate timing relative to the signals.
In high-speed serial communications, provision is made to avoid transmitting a clock signal as a separate signal from the communication data in order to reduce the number of communication lines. In order to correctly receive communication data transmitted from the transmission side, the data receiver unit recovers a clock signal based on the data stream of the received communication data, and recovers the data by latching the data in synchronization with the recovered clock signal. A circuit that recovers a clock signal and data signal in this manner is referred to as a clock and data recovery circuit.
FIG. 1 is a block diagram showing the configuration of a related-art receiver using a clock and data recovery circuit. A receiver 10 of FIG. 1 includes an amplifier 11, a sampler 12, a demultiplexer 13, a digital filter 14, and a multi-phase clock generator 15.
The amplifier 11 receives data transmitted from the transmission side, and amplifies the received data. The received data amplified by the amplifier 11 is supplied to the sampler 12. The sampler 12 samples the received data supplied from the amplifier 11 in synchronization with a plurality of clock signals (multi-phase clock signals) having the same frequency and different phases, which are supplied from the multi-phase clock generator 15. The example shown in FIG. 1 illustrates a case in which the received data is multiplexed data. The data that are sampled at different phases by the sampler 12 are demultiplexed by the demultiplexer 13.
The data sampled at different phases in the manner as described above have values responsive to the phase of the respective multi-phase clock signals generated by the multi-phase clock generator 15. The digital filter 14 performs filtering on the sampled data, thereby generating a digital code responsive to the timing relationships between the received data signal and the multi-phase clock signals generated by the multi-phase clock generator 15.
The multi-phase clock generator 15 receives an internal clock signal, and generates the plurality of clock signals having the same frequency and different phases based on the internal clock signal. In so doing, the multi-phase clock generator 15 adjusts the phase of the clock signals in response to the digital code supplied from the digital filter 14. This makes it possible to latch the data by using clock signals having the timings that match the received data.
FIG. 2 is a drawing showing an example of the configuration of the multi-phase clock generator 15. The multi-phase clock generator 15 of FIG. 2 includes a multi-phase clock generating unit 21, a phase controlling circuit 22, and a delay element line 23.
The multi-phase clock generating unit 21 uses an internal clock signal Clk as an input signal, and, based thereupon, generates k signals having different phases by use of a series of delay elements each having a delay of T/k relative to a clock cycle T as shown in FIG. 2. In order to divide one cycle exactly by k, PLL (phase locked loop) or DLL (delay locked loop) may be used.
The phase controlling circuit 22 adds up the multi-phase clock signals generated by the multi-phase clock generating unit 21 to obtain a weighted sum by assigning different weighting factors, thereby generating a clock signal having the phase indicated by the input digital code. The phase controlling circuit 22 may be implemented by use of a mixer circuit, for example. A mixer circuit may obtain a weighed sum of a sinusoidal wave having 0-degree phase and another sinusoidal wave having 90-degree phase by assigning different weighting factors (different amplitudes), thereby generating a sinusoidal wave having a desired phase between 0 degree and 90 degrees.
The clock signal having a desired phase generated by the phase controlling circuit 22 is supplied to the delay element line 23. The delay element line 23 uses the phase-adjusted clock signal supplied from the phase controlling circuit 22 as an input signal, and, based thereupon, generates 1 signals having different phases by use of a series of delay elements each having a delay of T/1 relative to the clock cycle T.
FIG. 3 is a signal waveform diagram showing the process by which multi-phase clock signals are generated. FIG. 3-(a) illustrates input data. A clock signal Clka having a 0-degree phase as shown in (b) and a clock signal Clkb having a 90-degree phase as shown in (c) are supplied to the phase controlling circuit 22 shown in FIG. 2. The phase controlling circuit 22 combines the clock signal Clka and the clock signal Clkb to generate a clock signal having a desired phase between 0 degree and 90 degrees. The clock signal having a desired phase generated in this manner is illustrated as a phase-adjusted clock signal in (d).
Based on the phase-adjusted clock signal shown in (d), multi-phase clock signals shown in (e) are generated. In this example, four multi-phase clock signals having respective phases of 0 degree, 90 degrees, 180 degrees, and 270 degrees are generated. These multi-phase clock signals are supplied to the sampler 12 (FIG. 1), which samples the input data by use of the individual clock signals.
In the configuration that uses a mixer circuit as the phase controlling circuit 22, the mixer circuit operates as will be described in the following. When the input clock signals are sinusoidal waves, the clock signal Clka having a 0-degree phase and the clock signal Clkb having a 90-degree phase are represented as:Clka=A sin(t)Clkb=B sin (t−π/2)Here, the amplitude of the clock signal Clka is A, and the amplitude of the clock signal Clkb is B. The mixer circuit adds up a plurality of sinusoidal wave electric signals to generate a single sinusoidal wave signal. When the clock signal Clka and the clock signal Clkb are added together, the following is obtained.Clka+Clkb=(A2+B2)1/2 sin(t−φ)  (1)φ=tan−1(B/A)  (2)In conventional mixer circuits, a reference current Ir is used, and the amplitude A is set to (Ir) (1−m/n), and the amplitude B is set to (Ir) (m/n). Namely, the amplitude A and the amplitude B are represented by a function that respectively decreases and increases linearly in response to m with a step size of an amplitude change being Ir/n. As m is increased one by one from zero to n, the amplitude A linearly decreases, and the amplitude B linearly increases. This makes it possible to increase the phase gradually from 0 degree to 90 degrees. This value m corresponds to the above-described digital code.
In the conventional mixer circuit as described above, the amplitude A and the amplitude B of the input sinusoidal waves are linearly changed. In this case, phase φ defined by the formula (2) does not change linearly.
FIG. 4 is a drawing showing phase values corresponding to respective digital codes. In FIG. 4, an interval from phase 0 to phase π/2 is assigned to the range of digital codes from 0 to 16, and the value of a phase represented by the formula (2) corresponding to each digital code is plotted. The illustrated stepwise characteristic line indicates an ideal situation in which the phase changes linearly in a stepwise manner in response to stepwise changes of the digital code. A chain line demonstrates an ideal situation in which the phase changes linearly as the step size of the digital code is further reduced.
In reality, phase φ defined by the formula (2) exhibits an S-shape curve characteristic as indicated by the dotted curved line. Namely, the rate of phase change relative to a change in the digital code becomes maximum around the center (π/4 in this example) of the range of phase change. Near the ends of the range of phase change (near 0 and near π/2), the rate of phase change relative to a change in the digital code becomes minimum. Namely, when A changes from 8/16 to 7/16, and B changes from 8/16 to 9/16, for example, a change in phase φ is relatively large. However, when A changes from 16/16 to 15/16, and B changes from 0/16 to 1/16, for example, a change in phase φ is relatively small. This may be intuitively understood by illustrating a sum of two phasors at a right angle to each other having amplitude A and amplitude B in the complex plane.
As described above, the size of phase change relative to a change in the digital code is not constant, and differs depending on what the current phase is. If the size of change is sometimes large and sometime small, the jitter of the clock signal becomes large when the size of change is large. Namely, if the digital code fluctuates due to process variation, noise, or the like, the phase of the phase-adjusted clock signal generated by the phase controlling circuit 22 fluctuates (suffers the occurrence of jitter). Depending on the position of the phase, the size of jitter can become larger than an ideal phase step size of the clock signal, which may cause error in the clock recovery operation and data recovery operation.
[Patent Document 1] Japanese Patent Application Publication No. 2003-8555.
Accordingly, there is a need for a phase controlling circuit in which the linearity of phase change relative to the digital code is improved.